Full CAN controllers can be configured to interrupt the CPU only when messages whose Identifiers have been setup as acceptance filters in the controller. Full CAN controllers are also setup with multiple message objects referred to as mailboxes, which can store specific message information such as ID and data bytes received for the CPU Ultrasonic sensor to retrieve. The CPU in this case would retrieve the message any time, however, must complete the task prior to an update of that same message is received and overwrites the current content of the mailbox. This scenario is resolved in the final type of CAN controllers.
– Extended Full CAN controller: provides an additional level of hardware implemented functionality, by providing a hardware FIFO for received messages. Such an implementation allows more than one instance of the same message to be stored before the CPU is interrupted therefore preventing any information loss for high frequency messages, or even allowing the CPU to focus on the main module function for a longer period of time.
Depending on the message architecture, the above 2 configurations can coexist in a single module, in order to implement high level message priority and improve received message handling for the CPU. For example, a module receiving failsafe information in one message (i.e. ID = 0x250) and temperature sensor information in another message (i.e. ID = 0x3FF) may configure the CAN controller as full for the first, and extended full with 4 buffer FIFO for the second: CPU is interrupted when each failsafe message is received, and once every 4 temperature sensor message received; CAN controller configuration with a visual CAN controller customizer for fast implementation of complex message handling schemes where all 3 types of CAN controllers co-exist:
– Message 5 – Basic CAN Mailbox.
– Message 0x250 – Full CAN Mailbox.
– Message 0x3FF – Extended Full CAN Mailbox.
In addition to its functional capabilities, CAN has been widely adopted for it high fault tolerance. With bit rates up to 1Mbps, or bus length up to 1000m (at 50Kbps), CAN bit timing must be implemented to allow functionality in electrically noisy environment while maintaining high level of failure detection and correction.
To guarantee a high level of fault tolerance, sub-bit timing configuration has been introduced with CAN to allow tighter control of determining the correct bus state for each CAN Bus.
A single CAN bit is represented by 4 segments:
– Sync_Seg: Used to synchronize the various nodes on the bus.
– Prop_Seg: Compensate for any physical delays (propagation delay on the physical bus and the internal CAN node.
– Phase_Seg1, Phase_Seg2: Used to compensate for phase edge errors. These segments are shortened of lengthened during resynchronization.